The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and particularly relates to a semiconductor device including a transistor using a high dielectric constant insulating film as a gate insulating film and a method for fabricating the semiconductor device.
As a design rule of a semiconductor device is scaled down, a degree of integration of a circuit is dramatically improved. Thus, more than hundred million field effect transistors (FETs) can be mounted on a single chip. In order to realize a high-performance transistor, not only reduction in gate length but also reduction in thickness of a gate insulating film are required. Conventionally, e.g., a silicon oxide film or a silicon oxynitride film which is a nitride film of the silicon oxide film has been used as the gate insulating film. However, if an equivalent oxide thickness (EOT) is reduced to equal to or less than about 2 nm, gate-leakage current is increased, thereby causing a problem that power consumption of the circuit is increased.
Increasing attention has been given to a high dielectric constant gate insulating film in order to reduce the gate-leakage current and reduce the EOT. A “high dielectric constant insulating film” means an insulating film having a dielectric constant higher than a dielectric constant (about 8.0) of a silicon nitride film.
In order to further reduce the EOT, a variety of techniques have been developed for a transistor in which a gate electrode using metal material such as titanium nitride and tantalum nitride is combined with a high dielectric constant gate insulating film, i.e., a transistor having a high dielectric constant gate insulating film/metal gate electrode structure, instead of a conventional gate electrode using silicon material.
One of challenges to realizing the high dielectric constant gate insulating film/metal gate electrode structure is control of threshold voltage of the transistor. In the conventional silicon electrode, a work function of the silicon electrode is adjusted by impurity ion implantation, thereby realizing threshold voltage suitable for each of an N-type FET and a P-type FET. That is, for the N-type FET, an attempt is made to reduce the work function by implanting an N-type impurity such as arsenic and phosphorus to the silicon electrode. On the other hand, for the P-type FET, an attempt is made to increase the work function by implanting a P-type impurity such as boron to the silicon electrode.
However, for the metal gate electrode, the work function cannot be controlled by the impurity ion implantation, and therefore the control of the threshold voltage of the transistor having the metal gate electrode is a great challenge.
As a method for controlling the work function of the transistor having the high dielectric constant gate insulating film/metal gate electrode structure, a method has been proposed, in which metal is added so that an electric dipole for reducing the threshold voltage can be formed at an interface between an oxide film on a surface of a semiconductor substrate and the high dielectric constant gate insulating film (see P. Sivasubramani et al., Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics, Symposium on VLSI Technology Digest of Technical Papers, 2007, pp. 68-69, and S. Kubicek et al., Strain Enhanced Low-VT CMOS Featuring La/Al-doped HfSiO/TaC and 10 μs Inventor Delay, Symposium on VLSI Technology Digest of Technical Papers, 2008, pp. 130-131).
FIG. 8A illustrates a configuration described in Sivasubramani et al., i.e., a configuration in a cross section of a transistor structure in which lanthanum is, as metal forming an electric dipole at an interface between an oxide film on a surface of a semiconductor substrate and a high dielectric constant gate insulating film, added to an N-type FET having a hafnium silicon oxynitride high dielectric constant gate insulating film/metal gate electrode structure. As illustrated in FIG. 8A, in the N-type FET disclosed in Sivasubramani et al., a high dielectric constant insulating film 502 made of hafnium silicon oxynitride (HfSiON) is stacked on a silicon oxide film 501 formed on a silicon substrate 500. In addition, a metal electrode 504 made of TiN is stacked on the high dielectric constant insulating film 502 with a metal oxide film 503 made of lanthanum (La) being interposed therebetween.
FIG. 8B illustrates a composition distribution (composition distribution in a direction perpendicular to a principal surface of the substrate) obtained by performing activation annealing for the high dielectric constant gate insulating film/metal gate electrode structure illustrated in FIG. 8A and diffusing lanthanum atoms. As illustrated in FIG. 8B, the lanthanum (La) atoms are diffused to an interface between the silicon oxide film (SiO2) 501 and the high dielectric constant gate insulating film 502 through the high dielectric constant gate insulating film (HfSiON) 502, and, as a result, the electric dipole can be formed at such an interface. This reduces threshold voltage of the N-type FET by about 230 mV. Note that, as illustrated in FIG. 8B, the lanthanum atoms are also diffused in the metal electrode (TiN) 504, and a lanthanum composition ratio (La concentration) is substantially the maximum at an interface between the metal electrode 504 and the high dielectric constant gate insulating film 502.
FIG. 9A illustrates a configuration in a cross section of a transistor structure described in Kubicek et al., and specifically illustrates a configuration in a cross section of a transistor structure in which a metal oxide film such as a lanthanum oxide film (N-type FET) and an aluminum oxide film (P-type FET) is stacked below a high dielectric constant gate insulating film, and therefore an electric dipole for reducing threshold voltage is formed at an interface between the oxide film on a surface of a semiconductor substrate and the high dielectric constant gate insulating film. As illustrated in FIG. 9A, in the FET disclosed in Kubicek et al., a high dielectric constant insulating film 502 made of hafnium silicon oxynitride (HfSiON) is stacked on a silicon oxide film 501 formed on a silicon substrate 500 with a metal oxide film 503 containing lanthanum (La) or aluminum (Al) being interposed therebetween. In addition, a metal electrode 504 made of TiN is stacked on the high dielectric constant insulating film 502. FIG. 9B illustrates a composition distribution (composition distribution in a direction perpendicular to a principal surface of the substrate) obtained by performing activation annealing for the high dielectric constant gate insulating film/metal gate electrode structure (in a case where the metal oxide film containing lanthanum (La) is used as the metal oxide film 503) illustrated in FIG. 9A and diffusing lanthanum atoms. As illustrated in FIG. 9B, the lanthanum atoms exist at an interface between the silicon oxide film (SiO2) 501 and the high dielectric constant gate insulating film (HfSiON) 502, and, as a result, the electric dipole can be formed at such an interface. This reduces the threshold voltage of the N-type FET by about 500 mV. Note that, as illustrated in FIG. 9B, the lanthanum atoms are also diffused in each of the silicon oxide film 501 and the high dielectric constant gate insulating film 502, and a lanthanum composition ratio (La concentration) is substantially the maximum at the interface between the silicon oxide film 501 and the high dielectric constant gate insulating film 502. If the metal oxide film containing aluminum (Al) is used as the metal oxide film 503, the threshold voltage of the P-type FET can be reduced by about 200 mV.